Modified fuse structure and method of use

ABSTRACT

An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.

BACKGROUND

In the semiconductor industry, fuse elements are used in integratedcircuit (IC) devices for a variety of purposes including, for example,improving manufacturing yield and/or customizing generic programmable ICdevices. For example, by isolating a defective circuit on an IC deviceor replacing the defective circuit with a redundant circuit provided onthe same IC device, manufacturing yields can be increased. Conversely,activating or deactivating certain of the functional elements providedon a generic programmable IC device design defines a customized ICdevice.

Because memory devices comprise large arrays of memory cells, the ICdevice designs include a number of memory cells that are activated ordeactivated using fuses (for cutting an electrical connection) and/orantifuses (for establishing an electrical connection) in order toreplace defective memory cells with corresponding and fully functionalreplacement memory cells. Replacing the defective memory cells increasesthe number of functional IC devices and, correspondingly, increases theoverall manufacturing yield. Similarly, generic IC device designs arecustomized by activating and/or deactivating various circuit elementsusing fuses and/or antifuses to produce programmed IC devices having adesired functionality.

Some One-Time-Programmable (OTP) devices, e.g., IC memory devices, usemetal fuses in which portions of a metal pattern are “blown” by applyingcurrent beyond that which the fuse element is able to handle, therebysevering an existing electrical connection and creating an “open”circuit that prevents electrical connection to the associated functionalelements. Other OTP memory devices, however, use gate oxide fuses inwhich gate oxide structures comprise the programming elements that are“blown” by applying excess voltage, thereby causing gate oxidebreakdown.

Whether the programming devices use metal fuses and/or gate oxideantifuses, however, the programming process typically involves applyinghigh voltage(s) in order to achieve the desired programming (e.g., whenusing gate oxide antifuses) or applying high currents (when using metalfuses). Such high voltages or high currents are taken into considerationduring the design phase to ensure that the high voltage and/or highcurrent used during the programming operation does not damage othercircuitry on the IC device. Additional considerations include, forexample, the complexity and the cost of fabricating the IC device andthe area of the IC device devoted to the programming circuit(s).

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1A is a schematic view of an antifuse structure according to someembodiments and FIG. 1B is a schematic view of the antifuse structure ofFIG. 1A after a programming operation.

FIG. 2 is a layout view of an antifuse structure according to someembodiments corresponding to functional elements of a antifuse structureaccording to FIG. 1A.

FIG. 3A is a layout view of a vertical antifuse structure according tosome embodiments, FIG. 3B is a layout view of a horizontal antifusestructure according to some embodiments, and FIG. 3C is across-sectional view of an antifuse structure according to someembodiments.

FIGS. 4A-4B are schematic views of IC devices incorporating an antifusestructure according to some embodiments.

FIGS. 5A and 6A are layout views of IC devices incorporating a pluralityof antifuse structures according to some embodiments and FIGS. 5B, 5C,and 6B are simplified layout views of the IC devices of FIGS. 5A and 6A.

FIGS. 7A-7C are schematic views of the programming and read operationsof an antifuse structure according to some embodiments.

FIG. 8 is a chart reflecting functional portions of a system formanufacturing IC devices incorporating the antifuse structure.

FIG. 9 is a flowchart showing the overlap between IC device design,manufacture, and programming.

DETAILED DESCRIPTION

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. The following disclosureprovides many different embodiments, or examples, for implementingdifferent features of the provided subject matter. Specific examples ofcomponents, values, operations, materials, arrangements, or the like,are described below to simplify the present disclosure.

These are, of course, merely examples and are not intended to belimiting. Other components, values, operations, materials, arrangements,or the like, are contemplated. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper,” “vertical,” “horizontal,” and the like, may be usedherein for ease of description to describe one element or feature'srelationship to another element(s) or feature(s) as illustrated in theFigures. The spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the Figures. The apparatus and structuresmay be otherwise oriented (rotated by, for example, 90°, 180°, ormirrored about a horizontal or vertical axis) and the spatially relativedescriptors used herein may likewise be interpreted accordingly.

The structures and methods detailed below relate generally to electricalfuses (fuses, e-fuses, and/or antifuses) and, particularly, to antifusedesigns and associated methods that can be utilized for programming ICdevices and, more particularly, to IC device designs incorporatingantifuse structures and methods for use OTP operations in which anapplied programming voltage degrades a dielectric material to establishan electrical connection between two adjacent conductor structures.

As used herein, the term “dielectric antifuse” refers to an antifusestructure which, in an as-manufactured condition, defines a capacitor inwhich the electrodes include a portion of a gate conductor structure(MG) formed over the gate oxide and an adjacent and opposing portion ofa source/drain contact structure (MD) formed over the S/D regions inwhich an interlayer dielectric (ILD) separating the portion of the gateconductor structure and the source/drain contact structure acts as thedielectric to define the capacitor. The antifuse structure is alsoalternatively referenced as an “mdfuse” or “MDfuse” to reflect theutilization of the source/drain contact structure as one of the antifuseelectrodes and the corresponding use of the ILD as the dielectric.During a programming operation, if a particular dielectric antifuse isto be activated in order to connect the associated circuitry, a voltage,e.g., VDDQ_(P), is applied across the gate conductor structure andadjacent source/drain conductor structure plates, with the value ormagnitude of VDDQ_(P) being sufficient to breakdown or degrade theintervening interlayer dielectric material to establish a directresistive electrical connection between the portion of the gateconductor structure and an adjacent source/drain conductor structure,thereby converting the capacitor into a resistor.

According to some embodiments, the dielectric antifuse structure and ICdevices incorporating the dielectric antifuse structure, by utilizing aless robust dielectric material relative to a gate dielectric, allowsthe size of the programming circuitry, the magnitude of the current,and/or the programming voltage to be reduced significantly relative toother one transistor one resistor (1T1R) fuse designs. Although thedielectric antifuse is considered an antifuse, i.e., programming andielectric antifuse structure creates an electrical connection, in someinstances the term “fuse” will be used for simplicity. In someembodiments, for instance, the dielectric antifuse structure consumes10% or less of the area of the programming circuitry when compared withthe area used in implementing fuse designs, thereby allowing for theaddition of more functional circuitry and/or a reduction in the size ofthe resulting IC device.

FIG. 1A is a schematic view of an as-manufactured IC structure accordingto some embodiments, specifically an IC structure having a dielectricantifuse structure 100. The dielectric antifuse structure 100 includesan antifuse element 112, which is configured as a capacitor with a firstplate defined by a first portion of a source/drain conductor structure108 electrically connected to the programming transistor 104, a secondplate defined by a first portion of a gate conductor structure 106 thatis electrically connected to a VDDQ supply and overlaps the firstportion of a source/drain conductor structure 108, with a capacitordielectric 107 (ILD) between the two plates of the fuse element 112. Insome embodiments, the programming transistor 104 is configured with thegate conductor structure 104 g being controlled by a word line 102 w(WL) the source region 104 s opposite the fuse element 112 beingconnected to a bit line (BL) 102 b. The fuse element 112 is arrangedbetween and connected to both the programming transistor 104 and a VDDQsupply from which the read voltage (VDDQ_(O)) and the higher programmingvoltage (VDDQ_(P)) are applied.

FIG. 1B is a schematic view of a programmed IC structure according tosome embodiments, specifically an IC structure having a dielectricantifuse structure 100′. As programmed, the fuse element 112 provided inthe dielectric antifuse structure 100 (FIG. 1A) has been subjected to avoltage level (VDDQ_(P)) sufficient to induce a breakdown in the portionof the capacitor dielectric 107 arranged between the overlappingportions of the first plate defined by the first portion of thesource/drain conductor structure 108 (MD) and the second plate definedby a first portion of a gate conductor structure 106 (MG), therebycreating a resistive direct electrical connection 116 between the twoplates of the original capacitor of fuse element 112.

FIG. 2 is a plan view of an IC structure design according to someembodiments of a dielectric antifuse structure. The dielectric antifusestructure includes a fuse element 112, which, as manufactured, isconfigured as a capacitor with a first plate defined by a first portionof a source/drain conductor structure 108, a second plate defined by afirst portion of a gate conductor structure 106 and an interlayerdielectric (ILD) material provided between the two plates of the fuseelement 112 as a capacitor dielectric 107 or, if programmed, a resistivedirect electrical connection 116. In some embodiments, the programmingtransistor 104 is configured with the gate conductor structure 104 gbeing controlled by a word line 102 w (WL). The fuse element 112 isarranged between, and electrically connected to, both the programmingtransistor 104 and a VDDQ power supply 208 for a programming voltage 102v (VDDQ_(P)) from which the operational (read) voltages (VDDQ_(O) orVDD) and programming voltage(s) (VDDQ_(P)) are supplied to the fuseelement 112 and the programming transistor 104.

FIGS. 3A and 3B are plan views of fuse elements 112 according to someembodiments, which, as manufactured, are configured as a capacitor witha first plate defined by a first portion of a source/drain conductorstructure 108 (MD), a second plate defined by a first portion of a gateconductor structure 106 and a portion of ILD material provided betweenthe overlapping lengths of the two plates of fuse element 112 as acapacitor dielectric 107 or, if programmed, a resistor. Depending on thedesign specifications of the IC device, the design rules applicable tothe design layout of the IC device, and the space available, the fuseelements 112 can be provided in a horizontal configuration, FIG. 3A, avertical configuration, FIG. 3B, or other any other configurationconsistent with the design rules.

In embodiments in which the fuse element 112 has been programmed, theresistance of the resulting connection is a function of the conductivityof the density of electrical connections established through the ILDmaterial, the spacing W between the source/drain conductor structure 108and the gate conductor structure 106 and the length L of the overlappingportions of the source/drain conductor structure 108 and the gateconductor structure 106.

FIG. 3C is a cross-sectional view of fuse element 112 and programmingtransistor 104 according to some embodiments, which, as manufacturedover an active area 101 (the area in which the transistors are formed)or a field region (not shown), are configured as a capacitor with afirst plate defined by a first portion of source/drain conductorstructure 108, a second plate defined by first portion of a gateconductor structure 106, which can include multiple layers 106 a, 106 bof conductive material(s) (polysilicon, silicide, silicide, etc.), andportion(s) of ILD material provided between the overlapping lengths ofthe source/drain conductor structure 108 and gate conductor structure106 plates of antifuse element 112 as a capacitor dielectric 107. Likethe gate conductor structure 106, in some embodiments, the capacitordielectric 107 includes more than one layer of material forming thecapacitor dielectric 107 a, 107 b, having a combined height H or, ifprogrammed, a resistive direct electrical connection 116 in programmedantifuse element 112. In some embodiments, the composition of thecapacitor dielectric 107 used in a first antifuse element and thecomposition of the dielectric material used in a second antifuse elementcan be different, thereby allowing an IC designer greater flexibilityregarding the performance of the antifuse elements in different regionsof an IC device.

The length of the first portion of the gate conductor structure 106 isdefined by the placement of poly cut lines 218 that serve to separatethe first portion of the gate conductor structure 106 from the remainderof a polysilicon pattern. The first portion of the gate conductorstructure 106 is, in turn, electrically connected to the VDDQ powersupply 208 through via 220. In some embodiments, the programmingtransistor 104 includes a corresponding multilayer gate conductorstructure 104 g, 104 g′, and source/drain conductor structures 104 d,104 s arranged on opposite sides of the gate conductor structure 106.The gate conductor structure 104 g, 104 g′ of the programming transistor104 is, in turn, electrically to a word line 102 w (WL) through via 103.In some embodiments, the gate conductor structure is formed bydepositing a metallic seed material on exposed surfaces of the activearea and/or field regions with one or more layers of conductivematerial(s) being formed or deposited over the seed layer. In someembodiments, portions of the conductive material(s) are removed bychemical mechanical polishing (CMP) and/or plasma etching to isolateportions of the conductive material and form a conductive pattern. Insome embodiments, upper portions of the gate conductor structures aretreated to form silicide or salicide regions for further reducing theresistance of the gate conductor structures. In some embodiments, thesource/drain conductor structures are formed by depositing or formingn-doped and/or p-doped silicon or polysilicon on opposite sides of thegate conductor structures.

FIGS. 4A and 4B are schematic views of an IC structure according to someembodiments, specifically an IC structure having at least two dielectricantifuse structures 100/100′ (unprogrammed/programmed) including both aantifuse element 112 and a programming transistor 104, with one or moredummy transistors 117 arranged between the dielectric antifusestructures 100/100′. In some embodiments, the dummy transistors areconfigured with the gate electrodes electrically connected to a “source”voltage 118 (VSS). The number of dummy transistors 117 is represented bya value “N,” with N=1 for the schematic in FIG. 4A and N=2 for theschematic in FIG. 4B. Designs with higher N values are generally lessefficient as a result of the amount of surface area dedicated for theprogramming circuitry that is not then available for building otherfunctional elements. Accordingly, N values greater than 2 or 3 arepossible, but have reduced efficiency.

FIG. 5A is a plan view of an IC structure design according to someembodiments of an IC device that includes a pair of dielectric antifusestructures 100 a, 100 b that share a common boundary or edge along oneside of the dielectric antifuse structures, in which dielectric antifusestructure 100 a and dielectric antifuse structure 100 b are offset fromeach other by an 180° rotation and share a common VDDQ power supply 208extending parallel with the adjacent sides of the dielectric antifusestructures. FIGS. 5B and 5C are simplified plan views of an IC structuredesign according to some embodiments of an IC device highlighting thespatial relationship between pairs of adjacent IC devices 200 a, 200 b,according to some embodiments.

In FIG. 5B, IC device 200 b is rotated 180° relative to IC device 200 aand abuts IC device 200 a along a minor edge of the IC devices 200 a,200 b each of which includes a corresponding dielectric antifusestructure 100 a, 100 b. In FIG. 5C, IC device 200 b is “mirrored” aboutaxis M-M′ relative to IC device 200 a and abuts IC device 200 a along aminor (shorter) edge of the IC devices 200 a, 200 b each of whichincludes an dielectric antifuse structure 100 a, 100 b.

FIG. 6A is a plan view of an IC structure design according to someembodiments of an IC device that includes four pairs of dielectricantifuse structures 100 a, 100 b with one of the pair of dielectricantifuse structures 100 a configured for programing circuitry directedto odd bits (bits 1, 3, 5, and 7) and the paired dielectric antifusestructures 100 b configured for programing circuitry directed to evenbits (bits 2, 4, 6, and 8). Each of the pairs of dielectric antifusestructures 100 a, 100 b share a common boundary or edge along a major(longer) side of the dielectric antifuse structure, in which dielectricantifuse structure 100 a and dielectric antifuse structure 100 b arerotationally offset from the paired dielectric antifuse structure 100 a,100 b by 180° or, alternatively, present a mirror image of the paireddielectric antifuse structure, and share a common VDDQ power supply 208that extends over at least a portion of each of the dielectric antifusestructures 100 a, 100 b. In FIG. 6B, IC device 200 b is “mirrored” aboutaxis M-M′ relative to IC device 200 a and abuts IC device 200 a along amajor (longer) edge of the IC devices 200 a, 200 b, each of whichincludes an dielectric antifuse structure 100 a, 100 b.

FIG. 7A is a schematic view of an as-manufactured IC structure accordingto some embodiments, specifically an IC structure having a dielectricantifuse structure 100. During a programming operation, a programmingsequence calculated to achieve the predetermined functionality of thefinal IC device is applied to the as-manufactured IC structure byconnecting selected functional circuitry through correspondingdielectric antifuse structures. The programming sequence determineswhich of the initially “open” fuse elements 112 will be exposed to aprogramming voltage (VDDQ_(P)) under conditions suitable for degradingthe dielectric material(s) in the fuse element 112 and creatingresistive direct electrical connection 116. At the completion of theprogramming operation, i.e., when all of the selected dielectricantifuse structures have been programmed and are functioning asresistors, the programmed IC device will have the predeterminedfunctionality and be ready for test and assembly operations.

FIG. 7B is a schematic view of an as-manufactured (and unprogrammed) ICstructure according to some embodiments, specifically an IC structure inwhich the dielectric antifuse structure 100 was not exposed to aprogramming voltage (VDDQ_(P)) during the programming operation. Becausethe initial fuse element 112 capacitor structure remains intact, duringa “READ” operation, the unprogrammed circuit will read as “open,” i.e.,will exhibit a negligible read current, and will be designated or readas a “0.”

FIG. 7C is a schematic view of a programmed IC structure according tosome embodiments, specifically an IC structure in which the programmeddielectric antifuse structure 100′ was exposed to a programming voltage(VDDQ_(P)) under conditions suitable for degrading the dielectricmaterial(s) found in the fuse element 112, the initial capacitorstructure now resembles a resistive direct electrical connection 116.Because the initial capacitor structure was degraded (suffered abreakdown) during the programming operation, during a “READ” operation,the programmed circuit will read as a resistor, i.e., will exhibit ameasureable read current, and will be designated or read as a “1”.

FIG. 8 is a block diagram of an electronic process control (EPC) system800, in accordance with some embodiments. Methods described herein ofgenerating cell layout diagrams, in accordance with one or moreembodiments, are implementable, for example, using EPC system 800, inaccordance with some embodiments. In some embodiments, EPC system 800 isa general purpose computing device including a hardware processor 802and a non-transitory, computer-readable, storage medium 804.Computer-readable storage medium 804, amongst other things, is encodedwith, i.e., stores, computer program code (or instructions) 806, i.e., aset of executable instructions. Execution of computer program code 806by hardware processor 802 represents (at least in part) an EPC toolwhich implements a portion or all of, e.g., the methods described hereinin accordance with one or more (hereinafter, the noted processes and/ormethods).

Hardware processor 802 is electrically coupled to computer-readablestorage medium 804 via a bus 818. Hardware processor 802 is alsoelectrically coupled to an I/O interface 812 by bus 818. A networkinterface 814 is also electrically connected to hardware processor 802via bus 818. Network interface 814 is connected to a network 816, sothat hardware processor 802 and computer-readable storage medium 804 arecapable of connecting to external elements via network 816. Hardwareprocessor 802 is configured to execute computer program code 806 encodedin computer-readable storage medium 804 in order to cause EPC system 800to be usable for performing a portion or all of the noted processesand/or methods. In one or more embodiments, hardware processor 802 is acentral processing unit (CPU), a multi-processor, a distributedprocessing system, an application specific integrated circuit (ASIC),and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium 804 is anelectronic, magnetic, optical, electromagnetic, infrared, and/or asemiconductor system (or apparatus or device). For example,computer-readable storage medium 804 includes a semiconductor orsolid-state memory, a magnetic tape, a removable computer diskette, arandom access memory (RAM), a read-only memory (ROM), a rigid magneticdisk, and/or an optical disk. In one or more embodiments using opticaldisks, computer-readable storage medium 804 includes a compact disk-readonly memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or adigital video disc (DVD).

In one or more embodiments, computer-readable storage medium 804 storescomputer program code 806 configured to cause the EPC system 800 (wheresuch execution represents (at least in part) the EPC tool) to be usablefor performing a portion or all of the noted processes and/or methods.In one or more embodiments, computer-readable storage medium 804 alsostores information which facilitates performing a portion or all of thenoted processes and/or methods. In one or more embodiments,computer-readable storage medium 804 stores process control data 808including, in some embodiments, control algorithms, process variablesand constants, target ranges, set points, programming control data, andcode for enabling statistical process control (SPC) and/or modelpredictive control (MPC) based control of the various processes.

EPC system 800 includes I/O interface 812. I/O interface 812 is coupledto external circuitry. In one or more embodiments, I/O interface 812includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen,and/or cursor direction keys for communicating information and commandsto hardware processor 802.

EPC system 800 also includes network interface 814 coupled to hardwareprocessor 802. Network interface 814 allows EPC system 800 tocommunicate with network 816, to which one or more other computersystems are connected. Network interface 814 includes wireless networkinterfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wirednetwork interfaces such as ETHERNET, USB, or IEEE-1364. In one or moreembodiments, a portion or all of noted processes and/or methods, isimplemented in two or more EPC systems 800.

EPC system 800 is configured to receive information through I/Ointerface 812. The information received through I/O interface 812includes one or more of instructions, data, programming data, designrules that specify, e.g., layer thicknesses, spacing distances,structure and layer resistivity, and feature sizes, process performancehistories, target ranges, set points, and/or other parameters forprocessing by hardware processor 802. The information is transferred tohardware processor 802 via bus 818. EPC system 800 is configured toreceive information related to a user interface (UI) through I/Ointerface 812. The information is stored in computer-readable medium 804as user interface (UI) 810.

EPC system 800 is configured to send information to and receiveinformation from fabrication tools 820 that include one or more of ionimplant tools, etching tools, coating tools, rinsing tools, cleaningtools, chemical-mechanical planarizing tools, testing tools, inspectiontools, transport system tools, and thermal processing tools that willperform a predetermined series of manufacturing operations to producethe desired integrated circuit devices. The information includes one ormore of operational data, parametric data, test data, and functionaldata used for controlling, monitoring, and/or evaluating the executionand progress of the manufacturing process. The information is stored inand/or retrieved from computer-readable medium 804.

In some embodiments, a portion or all of the noted processes and/ormethods is implemented as a standalone software application forexecution by a processor. In some embodiments, a portion or all of thenoted processes and/or methods is implemented as a software applicationthat is a part of an additional software application. In someembodiments, a portion or all of the noted processes and/or methods isimplemented as a plug-in to a software application. In some embodiments,at least one of the noted processes and/or methods is implemented as asoftware application that is a portion of an EPC tool. In someembodiments, a portion or all of the noted processes and/or methods isimplemented as a software application that is used by EPC system 800.

In some embodiments, the processes are realized as functions of aprogram stored in a non-transitory computer readable recording medium.Examples of a non-transitory computer readable recording medium include,but are not limited to, external/removable and/or internal/built-instorage or memory unit, e.g., one or more of an optical disk, such as aDVD, a magnetic disk, such as a hard disk, a semiconductor memory, suchas a ROM, a RAM, a memory card, and the like.

FIG. 9 is a block diagram of an integrated circuit (IC) manufacturingsystem 900, and an IC manufacturing flow associated therewith, inaccordance with some embodiments. In some embodiments, based on a layoutdiagram, at least one of (A) one or more semiconductor masks or (B) atleast one component in a layer of a semiconductor integrated circuit isfabricated using manufacturing system 900.

In FIG. 9, IC manufacturing system 900 includes entities, such as adesign house 920, a mask house 930, and an IC manufacturer/fabricator(“fab”) 950, that interact with one another in the design, development,and manufacturing cycles and/or services related to manufacturing an ICdevice 960. The entities in manufacturing system 900 are connected by acommunications network. In some embodiments, the communications networkis a single network. In some embodiments, the communications network isa variety of different networks, such as an intranet and the Internet.

The communications network includes wired and/or wireless communicationchannels. Each entity interacts with one or more of the other entitiesand provides services to and/or receives services from one or more ofthe other entities. In some embodiments, two or more of design house920, mask house 930, and IC Fab 950 is owned by a single larger company.In some embodiments, two or more of design house 920, mask house 930,and IC Fab 950 coexist in a common facility and use common resources.

Design house (or design team) 920 generates an IC design layout diagram922. IC design layout diagram 922 includes various geometrical patternsdesigned for an IC device 960. The geometrical patterns correspond topatterns of metal, oxide, or semiconductor layers that make up thevarious components of IC device 960 to be fabricated. The various layerscombine to form various IC features.

For example, a portion of IC design layout diagram 922 includes variousIC features, such as an active area, gate electrode, source and drainregions, metal lines or contacts/vias of an interlayer interconnection,and openings for bonding pads, to be formed in a semiconductor substrate(such as a silicon wafer) and various material layers disposed on thesemiconductor substrate. Design house 920 implements a proper designprocedure to form IC design layout diagram 922. The design procedureincludes one or more of logic design, physical design or place androute. IC design layout diagram 922 is presented in one or more datafiles having information of the geometrical patterns. For example, ICdesign layout diagram 922 can be expressed in a GDSII file format orDFII file format.

Whereas the pattern of a modified IC design layout diagram is adjustedby an appropriate method in order to, for example, reduce parasiticcapacitance of the integrated circuit as compared to an unmodified ICdesign layout diagram, the modified IC design layout diagram reflectsthe results of changing positions of conductive line in the layoutdiagram, and, in some embodiments, inserting to the IC design layoutdiagram, features associated with capacitive isolation structures tofurther reduce parasitic capacitance, as compared to IC structureshaving the modified IC design layout diagram without features forforming capacitive isolation structures located therein.

Mask house 930 includes mask data preparation 932 and mask fabrication944. Mask house 930 uses IC design layout diagram 922 to manufacture oneor more masks 945 to be used for fabricating the various layers of ICdevice 960 according to IC design layout diagram 922. Mask house 930performs mask data preparation 932, where IC design layout diagram 922is translated into a representative data file (“RDF”). Mask datapreparation 932 provides the RDF to mask fabrication 944. Maskfabrication 944 includes a mask writer. A mask writer converts the RDFto an image on a substrate, such as a mask (reticle) 945 or asemiconductor wafer 953. The IC design layout diagram 922 is manipulatedby mask data preparation 932 to comply with particular characteristicsof the mask writer and/or requirements of IC Fab 950. In FIG. 9, maskdata preparation 932 and mask fabrication 944 are illustrated asseparate elements. In some embodiments, mask data preparation 932 andmask fabrication 944 can be collectively referred to as mask datapreparation.

In some embodiments, mask data preparation 932 includes opticalproximity correction (OPC) which uses lithography enhancement techniquesto compensate for image errors, such as those that can arise fromdiffraction, interference, other process effects and the like. OPCadjusts IC design layout diagram 922. In some embodiments, mask datapreparation 932 includes further resolution enhancement techniques(RET), such as off-axis illumination, sub-resolution assist features,phase-shifting masks, other suitable techniques, and the like orcombinations thereof. In some embodiments, inverse lithographytechnology (ILT) is also used, which treats OPC as an inverse imagingproblem.

In some embodiments, mask data preparation 932 includes a mask rulechecker (MRC) that checks the IC design layout diagram 922 that hasundergone processes in OPC with a set of mask creation rules whichcontain certain geometric and/or connectivity restrictions to ensuresufficient margins, to account for variability in semiconductormanufacturing processes, and the like. In some embodiments, the MRCmodifies the IC design layout diagram 922 to compensate for limitationsduring mask fabrication 944, which may undo part of the modificationsperformed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation 932 includes lithographyprocess checking (LPC) that simulates processing that will beimplemented by IC Fab 950 to fabricate IC device 960. LPC simulates thisprocessing based on IC design layout diagram 922 to create a simulatedmanufactured device, such as IC device 960. The processing parameters inLPC simulation can include parameters associated with various processesof the IC manufacturing cycle, parameters associated with tools used formanufacturing the IC, and/or other aspects of the manufacturing process.LPC takes into account various factors, such as aerial image contrast,depth of focus (“DOF”), mask error enhancement factor (“MEEF”), othersuitable factors, and the like or combinations thereof. In someembodiments, after a simulated manufactured device has been created byLPC, if the simulated device is not close enough in shape to satisfydesign rules, OPC and/or MRC are be repeated to further refine IC designlayout diagram 922.

It should be understood that the above description of mask datapreparation 932 has been simplified for the purposes of clarity. In someembodiments, mask data preparation 932 includes additional features suchas a logic operation (LOP) to modify the IC design layout diagram 922according to manufacturing rules. Additionally, the processes applied toIC design layout diagram 922 during mask data preparation 932 may beexecuted in a variety of different orders.

After mask data preparation 932 and during mask fabrication 944, a mask945 or a group of masks 945 are fabricated based on the modified ICdesign layout diagram 922. In some embodiments, mask fabrication 944includes performing one or more lithographic exposures based on ICdesign layout diagram 922. In some embodiments, an electron-beam(e-beam) or a mechanism of multiple e-beams is used to form a pattern ona mask (photomask or reticle) 945 based on the modified IC design layoutdiagram 922. Mask 945 can be formed in various technologies. In someembodiments, mask 945 is formed using binary technology. In someembodiments, a mask pattern includes opaque regions and transparentregions. A radiation beam, such as an ultraviolet (UV) beam, used toexpose the image sensitive material layer (e.g., photoresist) which hasbeen coated on a wafer, is blocked by the opaque region and transmitsthrough the transparent regions. In one example, a binary mask versionof mask 945 includes a transparent substrate (e.g., fused quartz) and anopaque material (e.g., chromium) coated in the opaque regions of thebinary mask.

In another example, mask 945 is formed using a phase shift technology.In a phase shift mask (PSM) version of mask 945, various features in thepattern formed on the phase shift mask are configured to have properphase difference to enhance the resolution and imaging quality. Invarious examples, the phase shift mask can be attenuated PSM oralternating PSM. The mask(s) generated by mask fabrication 944 is usedin a variety of processes. For example, such a mask(s) is used in an ionimplantation process to form various doped regions in semiconductorwafer 953, in an etching process to form various etching regions insemiconductor wafer 953, and/or in other suitable processes.

IC Fab 950 includes wafer fabrication 952. IC Fab 950 is an ICfabrication business that includes one or more manufacturing facilitiesfor the fabrication of a variety of different IC products. In someembodiments, IC Fab 950 is a semiconductor foundry. For example, theremay be a manufacturing facility for the front end fabrication of aplurality of IC products (front-end-of-line (FEOL) fabrication), while asecond manufacturing facility may provide the back end fabrication forthe interconnection and packaging of the IC products (back-end-of-line(BEOL) fabrication), and a third manufacturing facility may provideother services for the foundry business.

Wafer fabrication 952 includes forming a patterned layer of maskmaterial formed on a semiconductor substrate is made of a mask materialthat includes one or more layers of photoresist, polyimide, siliconoxide, silicon nitride (e.g., Si₃N₄, SiON, SiC, SiOC), or combinationsthereof. In some embodiments, masks 945 include a single layer of maskmaterial. In some embodiments, a mask 945 includes multiple layers ofmask materials.

In some embodiments, the mask material is patterned by exposure to anillumination source. In some embodiments, the illumination source is anelectron beam source. In some embodiments, the illumination source is alamp that emits light. In some embodiments, the light is ultravioletlight. In some embodiments, the light is visible light. In someembodiments, the light is infrared light. In some embodiments, theillumination source emits a combination of different (UV, visible,and/or infrared) light.

Subsequent to mask patterning operations, areas not covered by the mask,e.g., fins in open areas of the pattern, are etched to modify adimension of one or more structures within the exposed area(s). In someembodiments, the etching is performed with plasma etching, or with aliquid chemical etch solution, according to some embodiments. Thechemistry of the liquid chemical etch solution includes one or more ofetchants such as citric acid (C₆H₈O₇), hydrogen peroxide (H₂O₂), nitricacid (HNO₃), sulfuric acid (H₂SO₄), hydrochloric acid (HCl), acetic acid(CH₃CO₂H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF),phosphoric acid (H₃PO₄), ammonium fluoride (NH₄F) potassium hydroxide(KOH), ethylenediamine pyrocatechol (EDP), TMAH (tetramethylammoniumhydroxide), or a combination thereof.

In some embodiments, the etching process is a dry-etch or plasma etchprocess. Plasma etching of a substrate material is performed usinghalogen-containing reactive gasses excited by an electromagnetic fieldto dissociate into ions. Reactive or etchant gases include, for example,CF₄, SF₆, NF₃, Cl₂, CCl₂F₂, SiCl₄, BCl₂, or a combination thereof,although other semiconductor-material etchant gases are also envisionedwithin the scope of the present disclosure. Ions are accelerated tostrike exposed material by alternating electromagnetic fields or byfixed bias according to methods of plasma etching that are known in theart.

In some embodiments, etching processes include presenting the exposedstructures in the functional area(s) in an oxygen-containing atmosphereto oxidize an outer portion of the exposed structures, followed by achemical trimming process such as plasma-etching or liquid chemicaletching, as described above, to remove the oxidized material and leavebehind a modified structure. In some embodiments, oxidation followed bychemical trimming is performed to provide greater dimensionalselectivity to the exposed material and to reduce a likelihood ofaccidental material removal during a manufacturing process. In someembodiments, the exposed structures may include the fin structures ofFin Field Effect Transistors (FinFET) with the fins being embedded in adielectric support medium covering the sides of the fins. In someembodiments, the exposed portions of the fins of the functional area aretop surfaces and sides of the fins that are above a top surface of thedielectric support medium, where the top surface of the dielectricsupport medium has been recessed to a level below the top surface of thefins, but still covering a lower portion of the sides of the fins.

IC Fab 950 uses mask(s) 945 fabricated by mask house 930 to fabricate ICdevice 960. Thus, IC Fab 950 at least indirectly uses IC design layoutdiagram 922 to fabricate IC device 960. In some embodiments,semiconductor wafer 953 is fabricated by IC Fab 950 using mask(s) 945 toform IC device 960. In some embodiments, the IC fabrication includesperforming one or more lithographic exposures based at least indirectlyon IC design layout diagram 922. Semiconductor wafer 953 includes asilicon substrate or other proper substrate having material layersformed thereon. Semiconductor wafer 953 further includes one or more ofvarious doped regions, dielectric features, multilevel interconnects,and the like (formed at subsequent manufacturing steps).

Once manufactured, however, IC device 960 designs that include efuseand/or antifuse structures will typically be subjected to a programmingoperation 980. During a programming operation, the IC design layoutdiagram 922 is used to develop a programming sequence during which aprogramming voltage (VDDQ_(P)) in excess of the designed operatingand/or input/output voltages (VDDQ, VDD) is applied to designateddielectric antifuses, causing the dielectric layer in the antifuseelement 112 to breakdown and form a resistive direct electricalconnection 116 as shown in, e.g., FIGS. 1B and 7C, for some embodiments.

For example, programmable read-only memory (PROM) devices have a grid ofcolumns and separated from a corresponding grid of rows in which everycolumn/row intersection (cell) includes an efuse connecting the twogrids. A charge sent through a column will pass through an intact efuseto a grounded row indicating a value of 1 for that particular cell.Because each of the cells has an efuse, the initial (blank) state of aPROM chip is all 1s. To change the value of a designated cell to 0, aprogramming device is used to send a specified programming currentthrough the cell. The programming current is sufficient to break theelectrical connection between the column and row of the designated cellby “burning out” the efuse in an operation frequently referred to as“burning” the PROM.

The efuse approach noted above in connection with PROM does not,however, scale well into deep submicron and/or FinFET processes, andsuch effuse structures consume a lot of device area to build thetransistors used in larger-capacity one-time programmable (OTP)non-volatile memory devices (NVM). In some embodiments, devicesutilizing the efuse approach suffer from high leakage currents instandby mode. And just as forced electromigration (EM) during theprogramming operation can “open” a metallic fuse, in some instances EMassociated with the subsequent operation of the programmed device causesefuses to reform an electrical connection, thereby corrupting theinformation initially programmed into the NVM. These drawbacks havecaused designers and foundries to look for alternatives.

The dielectric dielectric antifuse utilized in some embodiments, likeother antifuse-based OTP NVMs utilize differential oxide breakdownperformance to create its programming element, and can be incorporatedinto standard CMOS processes and device designs without requiringadditional process steps. In some embodiments, the antifuse elementsalso follow the same electrical and layout design rules as standardlogic circuits and is, therefore, scalable along with the otherfunctional structures comprising an IC device. The antifuse elements,therefore, benefit from the same yield and reliability gains as otherfunctional elements manufactured in accord with the improved performanceprovided by maturing process nodes while being readily adaptable for themost aggressive new process nodes.

Some antifuse OTP devices works by exploiting the parametric differencesbetween a thinner gate/core oxide and the thicker I/O oxide available instandard CMOS processes. The antifuse devices are programmed by applyinga high voltage to the gate, which causes the thinner core oxide to breakdown and create a short circuit. This process is robust and reliable,and unlike efuses, the oxide breakdown used to create the current pathdoes not suffer from regrowth or reconstitution over time. According tosome embodiments, an dielectric antifuse OTP IC device, however, worksby exploiting the dielectric qualities of the capacitor dielectric(s)107 (with the ILD materials being selected from, e.g., dielectrics,low-κ dielectrics, porous low-κ dielectrics, and combinations thereof)provided between a gate conductor structure 106, typically polysiliconand/or silicides/salicides, and an adjacent source/drain conductorstructure 108.

Unlike some prior art antifuse structures, the dielectric antifusestructure 100 does not involve breaking down the gate oxide/dielectriclayer(s). As a result of the ILD deposition techniques, the breakdownproperties of the ILD material can be modified to some degree bychanging the ILD material(s), the ILD deposition technique and/orconditions, and/or doping contained in the ILD material. Dielectricantifuse structures according to some embodiments are highly scalableand provide a degree of area efficiency significantly greater than thatof conventional efuse structures. In some embodiments, the surface areaused for the dielectric antifuse structure(s) is at least 90% less thanthe surface area that would be used for a corresponding efuse structure.The reduced area consumption of dielectric antifuse structures accordingto some embodiments allows for the manufacture of IC devices that uselower read power relative to IC devices utilizing conventional efusestructures to obtain the same IC device functionality.

Thus, IC Fab 950 at least indirectly uses IC design layout diagram 922to fabricate IC device 960. In some embodiments, semiconductor wafer 953is fabricated by IC Fab 950 using mask(s) 945 to form IC device 960. Insome embodiments, the IC fabrication includes performing one or morelithographic exposures based at least indirectly on IC design layoutdiagram 922. Semiconductor wafer 953 includes a silicon substrate orother proper substrate having material layers formed thereon.Semiconductor wafer 953 further includes one or more of various dopedregions, dielectric features, multilevel interconnects, and the like(formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g.,manufacturing system 900 of FIG. 9), and an IC manufacturing flowassociated therewith are found, e.g., in U.S. Pat. No. 9,256,709,granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 20150278429,published Oct. 1, 2015, U.S. Pre-Grant Publication No. 20140040838,published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21,2007, each of which are hereby incorporated, in their entireties, byreference.

In some embodiments, conductive lines are created within the integratedcircuit by depositing a layer of dielectric material on a layer of theintegrated circuit having gate structures therein, followed by formingan opening in the dielectric material at the location of at least onetrack. In some embodiments, metallic seed material is added to exposedsurfaces within the opening in the dielectric material and a layer ofconductive material is added to the opening over the seed layer. In someembodiments, the layer of conductive material is added byelectroplating. In some embodiments, the layer of conductive material isadded by sputtering, e.g., from a metal target. In some embodiments, thelayer of conductive material is added by chemical vapor deposition,including one or more of chemical vapor deposition (CVD),plasma-enhanced chemical vapor deposition (PECVD), atomic layerdeposition (ALD), and the like. In some embodiments, conductive materialon top of the layer of dielectric material is removed from the top ofthe layer of dielectric material by chemical mechanical polishing (CMP)and/or plasma etching to isolate portions of the conductive material inthe openings within the layer of dielectric material.

In some embodiments, the conductive lines along various tracks of theintegrated circuit layout or manufactured integrated circuit areseparated from each other, by removing a length of a conductive linebetween two other conductive lines, and filing the volume of the removedlength of conductive line with dielectric material (e.g., making atrench isolation structure between two conductive lines, wherein thetrench isolation structure and the conductive lines each extend alongthe first direction). In some embodiments, portions of one or moreadjoining conductive lines are isolated by etching through theconductive lines to form an insolation structure that extends in asecond direction different from the direction in which the conductivelines extend through the layer of the integrated circuit.

Active areas, or functional areas, or cells, of the integrated circuitdevice, are separated from each other or other elements of theintegrated circuit by the trench isolation structure between portions ofconductive lines in a region of the integrated circuit. In someembodiments, the conductive lines of the integrated circuit extendperpendicular to gate electrodes and the voltage-carrying or groundlines [VDD (primary drain voltage), VDDQ_(P) (programming drainvoltage), VDDQ_(O) (operational I/O drain voltage), and VSS (sourcevoltage)] of the cell of the IC device. In some embodiments, theconductive lines of the integrated circuit extend parallel to at leastone of the voltage-carrying lines of the integrated circuit, andparallel to the gate electrodes of the cell of the integrated circuit.

Some embodiments include an integrated circuit having a first dielectricantifuse electrode over an active area, a second dielectric antifuseelectrode over the active area and parallel to the first dielectricantifuse electrode, and a dielectric composition between the firstdielectric antifuse electrode and the second dielectric antifuseelectrode in which the first dielectric antifuse electrode, the seconddielectric antifuse electrode, and the dielectric composition form acapacitor. Some other embodiments also include a programming transistordirectly electrically connected to the second dielectric antifuseelectrode and a word line electrode electrically connected to a gateelectrode of the programming transistor. In some embodiments thedielectric composition is selected from a group consisting of low-κdielectrics, porous low-κ dielectrics, and combinations thereof, thefirst dielectric antifuse electrode comprises a first portion of apolysilicon gate structure, and the second dielectric antifuse electrodecomprises a first portion of a source/drain of the programmingtransistor. In some embodiments, the programming transistor iselectrically connected to a bit line, with the gate electrode beingarranged electrically between the bit line electrode and the seconddielectric antifuse electrode. In some embodiments, the dielectriccomposition will be characterized by a breakdown voltage that is lessthan a programming voltage.

Some embodiments include an integrated circuit structure having a firstdielectric antifuse structure on an active area, the first dielectricantifuse structure including a first dielectric antifuse electrode, asecond dielectric antifuse electrode extending parallel to the firstdielectric antifuse electrode, a first dielectric composition betweenthe first dielectric antifuse electrode and the second dielectricantifuse electrode, and a first programming transistor electricallyconnected to a first bit line electrode, a first word line electrode,and the second dielectric antifuse electrode and a second dielectricantifuse structure on the active area, the second dielectric antifusestructure including a third dielectric antifuse electrode, a fourthdielectric antifuse electrode extending parallel to the third dielectricantifuse electrode, a second dielectric composition between the thirddielectric antifuse electrode and the fourth dielectric antifuseelectrode, and a second programming transistor electrically connected toa second bit line electrode, a second word line electrode, and thefourth dielectric antifuse electrode. In some embodiments, the firstdielectric antifuse electrode is connectible to a programming voltage,the programming voltage being sufficient to induce a breakdown in thefirst dielectric composition and form an electrical connection betweenthe first dielectric antifuse electrode and the second dielectricantifuse electrode, and the third dielectric antifuse electrode isconnectible to the programming voltage, the programming voltage beingsufficient to induce a breakdown in second the dielectric compositionand form an electrical connection between the third dielectric antifuseelectrode and the fourth dielectric antifuse electrode. In someembodiments, a first dummy transistor is arranged between the firstprogramming transistor and the second programming transistor and, insome other embodiments, a second dummy transistor is arranged adjacentthe first dummy transistor. In some embodiments, the first bit lineelectrode and the second bit line electrode are combined in a common bitline electrode. In some embodiments, the first dielectric antifusestructure is rotated 180° relative to the second dielectric antifusestructure or the first dielectric antifuse structure is mirrored aboutan axis to define the second dielectric antifuse structure.

Some embodiments include a method for programming a semiconductor deviceincluding obtaining a semiconductor device having a number of integrateddielectric antifuse circuits, with each integrated dielectric antifusecircuit including a first dielectric antifuse electrode, a seconddielectric antifuse electrode adjacent and parallel to the firstdielectric antifuse electrode, a dielectric separating the firstdielectric antifuse electrode and the second dielectric antifuseelectrode to which a programming voltage is applied to a first set ofintegrated dielectric antifuse circuits, the programming voltage beingsufficient to induce breakdown of the dielectric and thereby form aresistive direct electrical connection between the first dielectricantifuse electrode and the second dielectric antifuse electrode of eachof the first set of integrated fuse circuits to obtain a programmedsemiconductor device. In other embodiments, a first dielectric antifuseelectrode is a first polysilicon structure formed on an active area anda second dielectric antifuse electrode is a second polysilicon structureformed on an active area adjacent and parallel to the first polysiliconstructure. In other embodiments, a spacing distance between the firstdielectric antifuse electrode and the second dielectric antifuseelectrode meets or exceeds a minimum source/drain to gate electrodespacing defined by a set of design rules used in designing and/ormanufacturing the other functional elements on the semiconductor device.In other embodiments, the first dielectric antifuse electrode is asource/drain contact structure and the second dielectric antifuseelectrode is a gate electrode structure. In other embodiments, themethod also includes conducting a functional test of the programmedsemiconductor device. In other embodiments, the dielectric is aninterlayer dielectric selected from a group consisting of dielectrics,low-κ dielectrics, porous low-κ dielectrics, and combinations thereof.In other embodiments, the second dielectric antifuse electrode is asource/drain contact structure of a programming transistor, theprogramming transistor being selected from a group consisting of NMOStransistors, PMOS transistors, and combinations thereof.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. An integrated circuit comprising: a first dielectric antifuseelectrode over an active area; a second dielectric antifuse electrodeover the active area and parallel to the first dielectric antifuseelectrode, a portion of the second dielectric antifuse electrodeoverlapping a portion of the first dielectric antifuse electrode; and adielectric composition provided between the overlapping portions of thefirst dielectric antifuse electrode and the second dielectric antifuseelectrode to form a dielectric antifuse structure.
 2. The integratedcircuit of claim 1, further comprising: a programming transistordirectly electrically connected to the second dielectric antifuseelectrode; and a word line electrode electrically connected to a gateelectrode of the programming transistor.
 3. The integrated circuit ofclaim 1, wherein: the dielectric composition is selected from a groupconsisting of low-κ dielectrics, porous low-κ dielectrics, andcombinations thereof.
 4. The integrated circuit of claim 2, wherein: thefirst dielectric antifuse electrode comprises a first portion of apolysilicon gate structure; and the second dielectric antifuse electrodecomprises a first portion of a source/drain of the programmingtransistor.
 5. The integrated circuit of claim 4, wherein: theprogramming transistor is electrically connected to a bit line, whereinthe gate electrode is electrically between the bit line and the seconddielectric antifuse electrode.
 6. The integrated circuit of claim 1,further wherein: the dielectric composition has a breakdown voltage,wherein the breakdown voltage is less than a programming voltage.
 7. Anintegrated circuit structure comprising: a first dielectric antifusestructure on an active area; wherein the first dielectric antifusestructure comprises: a first dielectric antifuse electrode, a seconddielectric antifuse electrode extending parallel to the first dielectricantifuse electrode, a first dielectric composition between the firstdielectric antifuse electrode and the second dielectric antifuseelectrode, and a first programming transistor electrically connected toa first bit line electrode, a first word line electrode, and the seconddielectric antifuse electrode; and a second dielectric antifusestructure on the active area; wherein the second dielectric antifusestructure comprises: a third dielectric antifuse electrode, a fourthdielectric antifuse electrode extending parallel to the third dielectricantifuse electrode, a second dielectric composition between the thirddielectric antifuse electrode and the fourth dielectric antifuseelectrode, and a second programming transistor electrically connected toa second bit line electrode, a second word line electrode, and thefourth dielectric antifuse electrode; and wherein when the firstdielectric antifuse electrode is connected to a programming voltage, theprogramming voltage induces a breakdown in the first dielectriccomposition and establishes an electrical connection between the firstdielectric antifuse electrode and the second dielectric antifuseelectrode, and wherein when the third dielectric antifuse electrode isconnected to the programming voltage, the programming voltage induces abreakdown in the second dielectric composition and establishes anelectrical connection between the third dielectric antifuse electrodeand the fourth dielectric antifuse electrode.
 8. The integrated circuitstructure according to claim 7, further comprising: a first dummytransistor between the first programming transistor and the secondprogramming transistor.
 9. The integrated circuit structure according toclaim 8, further comprising: a second dummy transistor adjacent thefirst dummy transistor.
 10. The integrated circuit structure accordingto claim 8, wherein: the first bit line electrode and the second bitline electrode comprise a common bit line electrode.
 11. The integratedcircuit structure according to claim 7, wherein: the first dielectricantifuse structure is rotated 180° relative to the second dielectricantifuse structure.
 12. The integrated circuit structure according toclaim 7, wherein: the first dielectric antifuse structure is mirroredabout an axis to define the second dielectric antifuse structure.
 13. Amethod for programming a semiconductor device comprising: obtaining asemiconductor device comprising a plurality of integrated dielectricantifuse circuits, wherein each of the integrated dielectric antifusecircuits comprises: a first dielectric antifuse electrode; a seconddielectric antifuse electrode adjacent and parallel to the firstdielectric antifuse electrode, a portion of the second dielectricantifuse electrode overlapping a portion of the first dielectricantifuse electrode; a dielectric separating the overlapping portions ofthe first dielectric antifuse electrode and the second dielectricantifuse electrode; and applying a programming voltage to a first set ofintegrated antifuse circuits, wherein the programming voltage induces abreakdown of the dielectric to form a resistive direct electricalconnection between the first dielectric antifuse electrode and thesecond dielectric antifuse electrode of each of the first set ofintegrated antifuse circuits to produce a programmed semiconductordevice.
 14. The method for programming a semiconductor device accordingto claim 13, wherein: the first dielectric antifuse electrode is a firstpolysilicon structure formed on an active area; and a second dielectricantifuse electrode is a second polysilicon structure formed on an activearea adjacent and parallel to the first polysilicon structure.
 15. Themethod for programming a semiconductor device according to claim 13,wherein: a spacing distance between the first dielectric antifuseelectrode and the second dielectric antifuse electrode meets a minimumsource/drain electrode to gate electrode spacing defined by a set ofdesign rules used in designing the semiconductor device.
 16. The methodfor programming a semiconductor device according to claim 13, wherein:the first dielectric antifuse electrode is a source/drain contact; andthe second dielectric antifuse electrode is a gate electrode structure.17. The method for programming a semiconductor device according to claim13, further comprising: conducting a functional test of the programmedsemiconductor device.
 18. The method for programming a semiconductordevice according to claim 13, wherein: the dielectric is an interlayerdielectric.
 19. The method for programming a semiconductor deviceaccording to claim 18, wherein: the dielectric is selected from a groupconsisting of dielectrics, low-κ dielectrics, porous low-κ dielectrics,and combinations thereof.
 20. The method for programming a semiconductordevice according to claim 18, wherein: the second dielectric antifuseelectrode is a source/drain contact structure of a programmingtransistor, the programming transistor being selected from a groupconsisting of NMOS transistors, PMOS transistors, and combinationsthereof.